The present invention relates to a communications system, and in particular to a multiple access digital communications system between a plurality of stations and a method of communicating data in such a system.
Consider a plurality of stations, such as digital computers. These computers may be interconnected to form a chain as shown in FIG. 1 of the accompanying drawings, in which each Station S.sub.1, S.sub.2 . . . S.sub.N is connected to a pair of lines 10, 11, with one line 10 (line A) carrying traffic in one direction and the other line 11 (line B) carrying traffic in the other direction. If a station such as station S.sub.1 wants to transmit data to a station further down the chain (i.e. to the right in FIG. 1) it can do this via line 10, and if it wishes to transmit data to a station higher up the chain (i.e. to the left in FIG. 1) it can transmit data via line 11. Equally, station S.sub.i receives data from stations higher up the chain via line 10 and from stations lower down the chain via line 11.
In order for such a system to operate efficiently, and for data collisions to be avoided, it is necessary to have a suitable protocol for transmitting data between the stations, and a known protocol for achieving this is discussed in U.S. Pat. No. 4,532,626.
In the protocol discussed in U. S. Pat. No. 4,532,626, the system operates by having the first station on each line (i.e. station S.sub.i, for line A and station S.sub.N for line B) act as a "head" station governing the generation of signals defining logical multi-bit frames that pass down the line and are usable by the stations to carry data. Each frame comprises an access control field and a data field. The operation of the system will now be discussed in more detail with reference to FIG. 2 of the accompanying drawings. In the following description it is assumed that the frames under consideration are passing down line A, but of course the situation is exactly analogous for line B.
The system operates cyclically in transporting data over line A in frames. As will become clear, within each system cycle, each station goes through a cycle of writing data to the frames. When all stations have completed their writing cycle, the system cycle terminates and new system and station cycles are thereafter commenced.
For the first frame in a system cycle, the head station sets the first bit of the access control field (which may thus be considered as a start bit), and the frame is then passed down the line. When the stations detect that start bit, they start their respective writing cycles and may thereafter seize (i.e. pass data in) any subsequent frame in which the data field is empty on arrival at that station. Each station transmits data by filling the data field of a seized frame with any one of the data packets which the station is to transmit (each data packet carries addressing information as well as the data to be passed). At the same time that the station fills the data field with a data packet the station sets a "busy" bit in the access control field of the frame to indicate to subsequent stations that the data field has been filled.
Thus, consider station S.sub.i. After initialization by the first frame from station S.sub.i in which the start bit is set, the station S.sub.i monitors the busy bit of subsequent frames. Where the busy bit of a frame is set, the station S.sub.i knows that a station further up the line has already filled the data field of that frame, and therefore the station S.sub.i cannot use that frame to pass information down the line. If, however, a frame arrives with the busy bit not set, the station S.sub.i can then fill the data field for passing data further down the line, and set the busy bit. Each station is arranged such that during each of its writing cycles it can transmit up to a predetermined maximum number of packets. System operation continues until all the stations have completed their writing cycles, that is, until they have transmitted their data packets, each up to their maximum permitted number of packets. When this happens, the next frame to pass down the line reaches the tail station S.sub.N with the busy bit empty. The tail station S.sub.N then realizes that the end of the system cycle has arrived, and passes a signal up the other line (i.e. line B) by setting an "end" bit in the access control field of the signal shown in FIG. 2. When that end bit reaches the head station S.sub.1, station S.sub.1 knows that all the stations down line A have completed their writing cycles and a new frame is sent out with the start bit set to recommence a system cycle for line A.
Thus, the operation of each station is as shown in FIG. 3. Where the station had no data packets to send, this is recorded in an appropriate memory and is indicated in FIG. 3 by the symbol AQ=0. This is known as the "idle" mode of the station. Where the station has data packets to send (i.e. AQ=0), the station moves into the "wait" mode in which it waits for an initializing signal from the head station, i.e. a signal in which the start bit has been set. When this happens, the station moves into the "defer" mode. In this mode each frame arriving at the station is checked to see if the busy bit is set, and if it is then the station remains in the defer mode. Where, however, the busy bit is not set, the station moves into the "access" mode in which subsequent frames are seized and data packets are transmitted down the line in the data fields of these frames. The station remains in the access mode as the data packets are sent until either data has been input to the predetermined maximum number of packets, in which case the station returns to the wait mode, or all the data packets have been sent so that the station has no more to send, in which case the station returns to the idle mode.
This operation is described as sequential, in that each station is gated so that where the station is already passing data packets to the data fields of frames on the line, any newly arriving data packet which the station determines must be transmitted will have to wait until the next cycle of frames before those newly arrived packets can be transmitted.
It is also possible for some or all the stations to operate in a non-gated mode so that if during a cycle the station has further packets to transmit over and above those already stored at the station at the start of the cycle, then the station can transmit those further packets provided that the total number of packets does not exceed the predetermined maximum number of packets.
The resulting passage of frames is shown generally in FIG. 4, in which it can be seen that when a system cycle starts, the data fields of subsequent frames are filled down the line until all the stations have sent the appropriate number of packets. There is then a delay while an unfilled frame passes down line A to the tail station and a frame with the end bit set passes up line B from the tail station to the head station; thereafter head station re-starts a system cycle. There is thus a delay between each group 12 of filled frames passing down the line.
This delay is thus a clear disadvantage of the system proposed in U.S. Pat. No. 4,532,626. The system is effectively not in use for the time it takes for a frame to pass from one end of the chain to the other and back, to indicate the start of a new system cycle.
In an article entitled "Description of Fasnet-A Unidirectional Local Area Communications Network", by J. O. Limb and C. Flores, in "The Bell System Technical Journal, Vol. 61, No. 7, Sep. 1982," the system proposed in U.S. Pat. No. 4,532,626 was discussed. In that article, on page 1428, there is the proposal that the system of U.S. Pat. No. 4,532,626 can be modified to allow some transmission during the delay time shown in FIG. 3. The proposal is that when any station detected a frame passing from the end station to the head station to signal the end of a system cycle (i.e. a frame in which the end bit is set as discussed previously), the station can begin transmission into frames on the other line in which the data fields are empty (signalled by the busy bit of the frame not being set). In this proposal, however, this transmission during the delay is only an interim feature, since the passage down one line of a frame in which the start bit is set re-initializes all the stations on that line. Thus, the modification discussed maintained the presence and action of the "head station" in relation to initiating the start of a new cycle.